1. SoC Design MANAGER (US) / Deputy Director (India)
Company Profile
Rezonent Corporation is on a mission is to recycle, reuse and thus radically reduce power and heat in semiconductor devices driving the entire digital world. For both the smartphone and data center end-markets, energy consumption, both useful and wasteful, as electricity and heat, is a major problem. Power bills and cooling costs now more than double the equipment costs for data centers and clouds. Trapped heat in smartphones reduces reliability and causes meltdowns. These two end-applications alone are a trillion-dollar market. Add in the future self-driving cars, Artificial Intelligence and Machine Learning (needing data centers that never sleep) and that number grows exponentially. Our solution leaves existing power management schemes in place and does not impact design flows or device performance. We believe the solution can shift the entire industry to 30% more energy efficient designs. To spearhead the deployment of this technology Rezonent is seeking an adventurous dynamic leader to go where no one has been before.
Job Summary
Hands-on Manages and Directs multiple SoC tape out projects concurrently from start to finish, handling all aspects of the projects within a timeframe and budget signed-off. If you also have a strong ability to explore innovative technologies and can demonstrate good problem-solving skills, this is the ideal position for you.
Key responsibilities & Tasks
- Lead the Silicon realization of LC resonance-based energy recycling patented IP of Rezonent
- DSM Library development in DSM including FinFETs for adoption by customers into future SoC
- On-time Tape out of bench-mark test chips and characterization for customer design wins
- Delivers results in time and within budget that exceed customer expectations
- First silicon success methodology development and risk management thereof
- Team building, development and retainment
- Contribute to the achievement of the aggressive objectives as stated in Rezonent Principles
- Support global team’s efforts with flexible times and places as needed
- Enable new product designs by understanding customer architectures and driving design requirements to meet customer use cases, standards, and regulations
- Ensure that the system level elements of next generation solutions (SOC, Software and board design) are optimized and trade-offs are well thought through
- Co-ordinate teams during pre-silicon and post-silicon validation, bring up and characterization
- Bridge FAE, Sales, R&D and third parties from an engineering perspective
- Support lead customers with bring-up and detailed training of our solutions
- Form and lead a team of 5 designers in 2018
- Lead fab technical interfaces for PDK, PCM etc.
- Train team to Design, simulate, and verify leading edge CMOS digital and analog circuits
- Supervise closely IC circuit/mask designers, provide floorplan and layout guidelines
- Support technology transfer to product development teams
- Support debug and characterization of design
Job Requirements
- Education/experience
- Min. 5 years industrial experience in Mixed Signal SoC/ IC design
- Min of 5 successful tape outs of production worthy products
- Min. 2 years relevant experience in project management
- Master’s Degree in Electrical Engineering (microelectronics preferred) or Ph.D. with 2 years
- Mandatory competences
- Technical: A thorough understanding of Digital and Analog integrated circuits
- Good understanding one of Major EDA Tool Flows such as Synopsys, Cadence or Mentor
- Custom IC design environment, circuit simulation (HSpice, Finesim etc.)
- Verilog and Digital design skills are a plus
- Personal skills
- Honesty and courage to communicate ‘bad news’ positively
- Excellent planning & organizing skills
- Superb time management skills
- Difficult decisions under pressure
- Establish work priorities and meet deadlines
- Predicting risks and Trouble-shooting problems
- Able to convince and buy-in people
- Team player able to motivate team members
- Strong communication and presentation skills
- Stress-resistant and result-oriented
- Willing to travel and be offsite for extended periods
- Fluency in English, both written and spoken
Offer
- Highly competitive customized compensation packages
- Making a difference in world with technology of societal impact
- Challenging environment, young and dynamic atmosphere.
- Opportunity to work in the challenging world-wide growth market
- Educational benefits & Development
- Reimburse relevant course work
- Sponsorship for PhD/post-doc programs
- Attendance to top IEEE conferences among others
You will gain global team leading experience working on state-of-art technology and acquire state-of-art-skill-sets pushing the limits of performance/power standards to save the planet. Rezonent also takes care of all special needs of talented work-force. We are an equal opportunity affirmative action employer.
2. Senior System Designer (USA & India)
Company Profile
Rezonent Corporation is on a mission is to recycle, reuse and thus radically reduce power and heat in semiconductor devices driving the entire digital world. For both the smartphone and data center end-markets, energy consumption, both useful and wasteful, as electricity and heat, is a major problem. Power bills and cooling costs now more than double the equipment costs for data centers and clouds. Trapped heat in smartphones reduces reliability and causes meltdowns. These two end-applications alone are a trillion-dollar market. Add in the future self-driving cars, Artificial Intelligence and Machine Learning (needing data centers that never sleep) and that number grows exponentially. Our solution leaves existing power management schemes in place and does not impact design flows or device performance. We believe the solution can shift the entire industry to 30% more energy efficient designs.
Job Summary
A senior ASIC digital design engineer who is analog aware. The candidate will have the opportunity to develop IP cores used in processor market specially for RISC-V and other ISAs like ARM, Tensilica. The candidate should have an MSEE completed at the time of joining as full-time employee. Candidates finishing their degree maybe offered internship leading to full time employment. The candidate must be willing to take ownership critical components for exciting, state of the art projects in the explosive data-center, cloud, AI and machine learning space offering lowest power semiconductor solutions. The candidate should enjoy working with a global team under pressure to beat the competition. This can be a once-in-a-lifetime opportunity for the right candidate and can rapidly lead to larger responsibilities and rewards. Compensation will match experience, degree, motivation and drive. Entry levels considered provide they have a strong course work and relevant project experience background.
Key responsibilities & Tasks
- SoC Design services for use of Library Cells using patented IP of Rezonent
- Qualification of Library development in DSM including FinFETs for adoption by customers
- Support Tape out of bench-mark test chips and characterization for customer design wins
- Delivers results in time as per MBOs (Management By Objectives)
- Verilog modelling and Regression analysis for First silicon success methodology development
- Contribute to the achievement of the aggressive objectives as stated in Rezonent Principles
- Support global team’s efforts with flexible times and places as needed
- Synthesis and verification of SoC with custom flows developed
- APR and floorplan and layout guideline
- Support technology transfer to product to development teams
- Debug and characterization of design
- Developing System Architecture and/or module level Microarchitecture specifications
Job Requirements
- Education/experience
- Candidate must have a BSEE with 5 yrs or MSEE with 2 years
- ASIC design and verification experience on job or with credited projects
- Actual DSM tape out experience a HUGE plus
- Track record using flow in Synopsys/Cadence for CMOS DSM technologies
- Hands-on experience with Verilog RTL coding and debug
- Problem solving and analytical skills
- FPGA prototype debug and system bring up skills
- Expertise with debug equipment such as analysers and scopes
- Expertise in ISA architecture like RISC-V a plus
- Good written and spoken communication skills and technical documentation skills
- Technical leadership and project management skills
Offer
- Highly competitive customized compensation packages
- Making a difference in world with technology of societal impact
- Challenging environment, young and dynamic atmosphere.
- Opportunity to work in the challenging world-wide growth market
- Educational benefits & Development
- Reimburse relevant course work
- Sponsorship for PhD/post-doc programs
- Attendance to top IEEE conferences among others
You will gain global team experience working on state-of-art technology and acquire state-of-art-skill-sets pushing the limits of performance/power standards to save the planet. Rezonent also takes care of all special needs of talented work-force. We are an equal opportunity affirmative action employer.
3. Circuit Designer Mixed Signal CMOS (USA & India)
Company Profile
Rezonent Corporation is on a mission is to recycle, reuse and thus radically reduce power and heat in semiconductor devices driving the entire digital world. For both the smartphone and data center end-markets, energy consumption, both useful and wasteful, as electricity and heat, is a major problem. Power bills and cooling costs now more than double the equipment costs for data centers and clouds. Trapped heat in smartphones reduces reliability and causes meltdowns. These two end-applications alone are a trillion-dollar market. Add in the future self-driving cars, Artificial Intelligence and Machine Learning (needing data centers that never sleep) and that number grows exponentially. Our solution leaves existing power management schemes in place and does not impact design flows or device performance. We believe the solution can shift the entire industry to 30% more energy efficient designs.
Job Summary
CMOS design engineer with Analog design expertise as well as mixed-signal design capabilities. The candidate should have a BSEE/MSEE completed at the time of joining as full-time employee. Candidates finishing their degree maybe offered internship leading to full time employment. The candidate must be willing to take ownership critical components for exciting, state of the art projects in the explosive data-center, cloud, AI and machine learning space offering lowest power semiconductor solutions. The candidate should enjoy working with a global team under pressure to beat the competition. This can be a once-in-a-lifetime opportunity for the right candidate and can rapidly lead to larger responsibilities and rewards. Compensation will match experience, degree, motivation and drive. Entry levels considered provide they have a strong course work and relevant project experience background.
Key responsibilities & Tasks
- Silicon realization of LC resonance-based energy recycling patented IP of Rezonent
- DSM Library development in DSM including FinFETs for adoption by customers into future SoC
- Tape out of bench-mark test chips and characterization for customer design wins
- Delivers results in time as per MBOs (Management By Objectives)
- First silicon success methodology development
- Contribute to the achievement of the aggressive objectives as stated in Rezonent Principles
- Support global team’s efforts with flexible times and places as needed
- Design, simulate, and verify leading edge CMOS digital and analog circuits
- Hands-on supervise closely IC circuit/mask designers, provide floorplan and layout guidelines
- Support technology transfer to product development teams
- Debug and characterization of design
Job Requirements
- Education/experience
- 1-5+ years design/RA/project experience in CMOS Analog/Mixed Signal Circuit Design
- Strong fundamental understanding of transistor devices and analog transistor level design
- Hands on design experienced in Giga-bit circuits and subsystems: oscillator, biasing circuits, bandgap references, regulators, op-amps and high-speed clocking circuits.
- PLL, DLL, transmitters, receivers, equalization a PLUS
- Experience in usage of IC design tools like Synopsys / Cadence for Analog Circuit Design
- Circuit Simulation, System Simulation
- Layout design, Physical Design, Physical Verification, Parasitic Extraction and Full Chip Verification
- Scripting Skills (Perl) as well as modelling and design skills in Verilog/Verilog AMS
- Will be required to work independently with limited supervision and be a team player
- MSEE will be considered as extra 2 years of experience and eligible for Senior Positions
Offer
- Highly competitive customized compensation packages
- Making a difference in world with technology of societal impact
- Challenging environment, young and dynamic atmosphere.
- Opportunity to work in the challenging world-wide growth market
- Educational benefits & Development
- Reimburse relevant course work
- Sponsorship for PhD/post-doc programs
- Attendance to top IEEE conferences among others
You will gain global team experience working on state-of-art technology and acquire state-of-art-skill-sets pushing the limits of performance/power standards to save the planet. Rezonent also takes care of all special needs of talented work-force. We are an equal opportunity affirmative action employer.
